7 ms·

They are basically acquiring talent and/or preexisting IP. RISC-V is free but implementations are the sole IP of the company. Implementing ARM and RISC-V decod

by 6SixTy 9mo ago

They are basically acquiring talent and/or preexisting IP. RISC-V is free but implementations are the sole IP of the company. Implementing ARM and RISC-V decoders might depend on licensing fine print for each licensee

Zhyl 9mo ago
This. SiFive, for example, is a proprietory core design based on the open source RISC V spec. Hazard3 [0] on the other hand, is an open source core design. [0] https://github.com/Wren6991/Hazard3 https://github.com/Wren6991/Hazard3
- jrepinc 9mo ago
  Another opensource core design is XiangShan https://xiangshan.cc/en/ https://xiangshan.cc/en/
- disdi 9mo ago
  Another opensource is https://github.com/SpinalHDL/VexRiscv https://github.com/SpinalHDL/VexRiscv
deleted 9mo ago
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