5 ms·
To be more precise, four CPUs - two ARM and two RISC. There is just a mux for the instruction and data buses - see chapter 3 of the [datasheet](https://datashee
by dcan 2y ago
To be more precise, four CPUs - two ARM and two RISC. There is just a mux for the instruction and data buses - see chapter 3 of the [datasheet](https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...).
It’s space-inefficient as half of the CPUs are shutdown, but architecturally it’s all on the same bus.
- Narishma 2y agoIt may be technically space inefficient but they only added the RISC-V cores because they had area to spare. It didn't cost them much.
- petertodd 2y agoI wonder if they're using the same die for one or more microprocessor products that are RISC-V-only or ARM-only? They could be binning dies that fail testing on one or the other cores that way. Such a product might be getting sold under an entirely different brand name too.
- baby_souffle 2y agoThat may be the plan for the future. Right now, this is a hedge / leverage against negotiations with ARM. For developers looking to test their code against a new architecture and compare it to known good code/behavior, it doesn’t get any easier than rebooting into the other core!
- jsheard 2y agoThey're not currently doing that but there is a documented way to permanently disable the ARM cores, so they could sell a cheaper RISC-V-only version of the same silicon if there's enough demand to justify another SKU.
- enragedcacti 2y agoSource for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used): > The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. https://nitter.space/wren6991/status/1821582405188350417 https://nitter.space/wren6991/status/1821582405188350417
- Graziano_M 2y agoFunny thing is that it cost them more than you might think. It was the ability to switch to the riscv which made it (much) easier to glitch. See the "Hazardous threes" exploit [1] [1] https://www.raspberrypi.com/news/security-through-transparency-rp2350-hacking-challenge-results-are-in/ https://www.raspberrypi.com/news/security-through-transparen...
- myrmidon 2y agoI find this whole concept remarkable, and somewhat puzzling. Have seen the same (ARM + RISC-V cores) even at larger scales before (Milk-V Duo @1GHz-ish). But how is this economical? Is die space that cheap? Could you not market the same thing as quadcore with just minor design changes, or would that be too hard because of power budget/bus bandwidth reasons?
- bananapub 2y agotwo things: 1) it needs a certain perimeter to allow all the pins to go from the silicon to the package, which mandates a certain sized square-ish die 2) only the cores are duplicated (and some switching thing is added) so yes, there is enough space to just add another two cores without any worries, since they don't need more IO or pins or memory or anything.
- imtringued 2y agoSRAM is very area intensive. What you're asking for is very greedy. The RISC-V core they are using is absolutely tiny.
- myrmidon 2y agoThats also a good point. For the big Milk-V systems I mentioned they use external DRAM-- but cache might still be a die-space issue (I'd assume that it's always shared completely between ARM/RISC-V cores, and would need to be scaled up for true multicore operation). But I'm still amazed that this is a thing, and you can apparently just throw a full core for a different architecture on a microcontroller at basically no cost :O
- Aurornis 2y ago> It’s space-inefficient as half of the CPUs are shutdown In practice is doesn't matter very much for a design like this. The size is already limited to a certain minimum to provide enough perimeter area to provide wire bonding area for all of the pins, so they can fill up the middle with whatever they want.
- DrNosferatu 2y agoThey should have filled it with more SRAM instead - 520KB is far too little.
- Tharre 2y agoWhat difference would the extra 16KiB or whatever instead of the 2 RISC-V cores make? If 520KB is far too little for you, you're likely better off adding a 8 MiB PSRAM chip.
- DrNosferatu 2y agoJust 16KB? Couldn’t a lot more be fitted? PSRAM has huge latency.
- DrNosferatu 1y agoThanks for the explanations - was not aware. …vertically stack a slab of SRAM above or beneath the CPU die, does come to mind ;)
- murderfs 1y agoThis is way too expensive for something like a microcontroller. AMD calls this 3D V-Cache and uses it on their top end SKUs.
- DrNosferatu 1y agoBut doesn't the ESP32-S3-WROOM have some large on-chip RAM? For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.