6 ms·
It uses https://github.com/alexforencich/verilog-pcie https://github.com/alexforencich/verilog-pcie on top of the Xilinx PCIe hard IP core, which provides every
by alexforencich 2y ago
It uses https://github.com/alexforencich/verilog-pcie https://github.com/alexforencich/verilog-pcie on top of the Xilinx PCIe hard IP core, which provides everything below the transaction layer.