No it pretty much is true, well it's the power draw from switching transistors and from leakage losses. Resistance in the metal wires is not so much a problem

No it pretty much is true, well it's the power draw from switching transistors and from leakage losses. Resistance in the metal wires is not so much a problem for power as it is for signal propagation delay. That is the biggest problem with R skyrocketing in M0/1. And backside power delivery is to relieve congestion in the interconnects. That's typically one of the limiting factors in complex logic designs now, transistor densities of under 70% aren't uncommon. That's what "Removing the power signal and signal line to just a signal line would free up space for more transistors." line is about in the link. Power delivery losses aren't nothing, but they aren't a big fraction of energy in today's CPUs. Eliminating most wire delay would be a huge benefit though, and could be a pretty big revolution. Not just within the core or on the die. You're still going to have to switch those transistors and burn current on leakage though, so no cold CPUs just yet.