5 ms·

As I posted in a comment on the article, he seems to have unrealistic expectations for an x86 assembler. TI's DSPs have a nice assembly because of their archit

by docmach 17y ago

As I posted in a comment on the article, he seems to have unrealistic expectations for an x86 assembler. TI's DSPs have a nice assembly because of their architecture. The x86 architecture is too complicated and the implementations too diverse to have an assembler like he wants.

tptacek 17y ago
Not so much: http://cr.yp.to/qhasm.html http://cr.yp.to/qhasm.html The version of our Ruby x86 assembler on my desk does register allocation as well.
- jwr 17y ago
  Cool! This is exactly what I had in mind. I didn't know about this project. Unfortunately, it seems to have been abandoned...
  - tptacek 17y ago
    It's not abandoned; DJB continues to use it in his crypto papers. But it's not really a standalone project yet.
jwr 17y ago
I'd put it another way: on VLIW DSPs they HAD to provide a good assembler, or they would be too difficult to program. From what I remember on some of them you have to manually manage the pipeline -- e.g. a jump instruction needs to occur several instructions BEFORE the actual jump, because by the time that instruction gets executed, several instruction after it will already have been decoded. You really don't want to do that manually. The only non-DSP processor I know that required programmers to schedule jumps ahead of time manually was the Intel i860, and it WAS too difficult to program, that's why it disappeared.