4 ms·

Again, I'm not seeing why it was 33kHz exactly. It sounds like OP just used the wrong prefix.

• tcas 11y ago
  I think it was just lowering the number by a few orders of magnitude to compensate for the effects and logic propagation delay (e.g. I think he said he's using a ripple adder which has a critical path dependent on the bit length), not a precise calculation exact number. My gut instinct says it's probably the right order of magnitude though. You could probably run the long stretches at a much higher clock rate or make the design run on asynchronous clock domains if you use good serialize/deserialize units.