4 ms·
Are you talking about this paper? https://gmplib.org/~tege/x86-timing.pdf https://gmplib.org/~tege/x86-timing.pdf I only saw evidence of data-dependent timing
by sdevlin 11y ago
Are you talking about this paper? https://gmplib.org/~tege/x86-timing.pdf https://gmplib.org/~tege/x86-timing.pdf
I only saw evidence of data-dependent timing with respect to the div operation, but maybe I missed something.
Of course, I am not suggesting other operations are inherently immune to data-dependent timing leaks.
EDIT: I see there are also some notes on adc and sbb in some situations, i.e. chains of instructions that all light up the carry flag.
- raverbashing 11y agoDon't worry about the instruction, worry about dest, src. If they: - Are in cache - Were touched by a previous instruction (regardless of cache) - Their cache line was touched by a previous instruction - Will be read/write (immediately) after that instruction - You're accessing data shared by multiple cores (lock prefix) timing will vary
- sdevlin 11y agoThat's the whole point, though - the algorithm is very straightforward to implement without data-dependent look-ups. So while any of those could affect execution time, none should do so in a way that leaks data.