5 ms·

The Real Story of the Write-Only-Memory

48 points by joe_bleau 12y ago

jontro 12y ago
Looks like a perfect backing device for /dev/null
- jpmattia 12y ago
  /dev/random gets all the attention, it's high time for a /dev/null hardware implementation.
  - arfar 12y ago
    There is /dev/null as a service: http://devnull-as-a-service.com/ http://devnull-as-a-service.com/
  - TazeTSchnitzel 12y ago
    Before that, even, it's very concerning that chroot()-jailed applications cannot access /dev/null in 2014!
- D-Coder 12y ago
  By coincidence, I happen to have backups of /dev/null. Of every computer, every nanosecond since the beginning of the Universe. From this and all possible Universes.
jcr 12y ago
The following pdf is roughly the same as the one linked in the article, but has better formatting/ocr so it tends to be more effective when trolling your favorite EE friends. http://repeater-builder.com/molotora/gontor/25120-bw.pdf http://repeater-builder.com/molotora/gontor/25120-bw.pdf
deleted 12y ago
[deleted]
TazeTSchnitzel 12y ago
Oh goodness, this press release. > Dr. Morris Breakthrough, a consultant on leave from Uisge Beatha, Ltd., of Kirkcudbrightshire, Scotland I lost it.
vardump 12y ago
"Lawson’s contributions too as he was a real comedian with lots of semiconductor experience. He could have invented the WOM concept. He did invent the “SCROM”. I doubt if any one else knows what that is. I’ll add later." "SCROM" must mean Self-Clear Read-Only Memory?
- tasty_freeze 12y ago
  It is related to the Self Contained Read Only Temporally Unified Memory.
trsohmers 12y ago
The concept of WOM isn't completely pointless for non von Neumann architectures, and could even be useful for von Neumann-esque SPMD or MPMD systolic array (http://en.wikipedia.org/wiki/Systolic_array http://en.wikipedia.org/wiki/Systolic_array) architectures that have strict execution models forced in the core to core wiring. While not completely free form, you would still have instructions and data being stored in the same space, it would be only readable by the individual PU is corresponds to. That PU would not write-back to that same memory, and instead could only write to an adjacent PU's memory, which then would only be readable (and not writable) by that next PU in the line. I've been wanting to implement such an architecture on an FPGA for a while now... may do so over this winter break.
- whitten 12y ago
  How do you implement this kind of thing in an FPGA ? It sounds intriguing.
nvader 12y ago
> If the device fails, you have exceeded the ragings. Minor typo, or anachronistic use of early 21st Century slang that suggests time traveller activity?
danjayh 12y ago
Reminds me of the retro encabulator (which was actually a video, not a data sheet) https://www.youtube.com/watch?v=NpnEiOOfu1Q https://www.youtube.com/watch?v=NpnEiOOfu1Q "The line-up consisted simply of six hydrocoptic marzul vanes so fitted to the ambaphascient lunar wain shaft that side fumbling was effectively prevented." Ahhh, classic.
- JonnieCache 12y ago
  https://www.youtube.com/watch?v=noSOFIJdfwM https://www.youtube.com/watch?v=noSOFIJdfwM
robert_tweed 12y ago
Perhaps not write-only memory per se, but write-only registers are a pretty common thing if you do any hardware-level programming. Though admittedly this isn't something I've done for a number of years, IIRC both the VGA and the original Sound Blaster had write-only registers which you would use to request some change in state, and some other registers that would reflect the actual current state of the device if/when the request was honoured. Of course these are not write-only in the sense that nothing can read their contents, since they are provided as an interface to some coprocessor like a GPU or a sound chip. That coprocessor can of course read the incoming data. They are more like the hardware equivalent of mutator methods on top of private properties.

48 points by joe_bleau 12y ago

jontro 12y ago

Looks like a perfect backing device for /dev/null

jpmattia 12y ago
/dev/random gets all the attention, it's high time for a /dev/null hardware implementation.
- arfar 12y ago
  There is /dev/null as a service: http://devnull-as-a-service.com/ http://devnull-as-a-service.com/
- TazeTSchnitzel 12y ago
  Before that, even, it's very concerning that chroot()-jailed applications cannot access /dev/null in 2014!
D-Coder 12y ago
By coincidence, I happen to have backups of /dev/null. Of every computer, every nanosecond since the beginning of the Universe. From this and all possible Universes.

jcr 12y ago

The following pdf is roughly the same as the one linked in the article, but has better formatting/ocr so it tends to be more effective when trolling your favorite EE friends. http://repeater-builder.com/molotora/gontor/25120-bw.pdf http://repeater-builder.com/molotora/gontor/25120-bw.pdf

deleted 12y ago

[deleted]

TazeTSchnitzel 12y ago

Oh goodness, this press release. > Dr. Morris Breakthrough, a consultant on leave from Uisge Beatha, Ltd., of Kirkcudbrightshire, Scotland I lost it.

vardump 12y ago

"Lawson’s contributions too as he was a real comedian with lots of semiconductor experience. He could have invented the WOM concept. He did invent the “SCROM”. I doubt if any one else knows what that is. I’ll add later." "SCROM" must mean Self-Clear Read-Only Memory?

tasty_freeze 12y ago
It is related to the Self Contained Read Only Temporally Unified Memory.

trsohmers 12y ago

The concept of WOM isn't completely pointless for non von Neumann architectures, and could even be useful for von Neumann-esque SPMD or MPMD systolic array (http://en.wikipedia.org/wiki/Systolic_array http://en.wikipedia.org/wiki/Systolic_array) architectures that have strict execution models forced in the core to core wiring. While not completely free form, you would still have instructions and data being stored in the same space, it would be only readable by the individual PU is corresponds to. That PU would not write-back to that same memory, and instead could only write to an adjacent PU's memory, which then would only be readable (and not writable) by that next PU in the line. I've been wanting to implement such an architecture on an FPGA for a while now... may do so over this winter break.

whitten 12y ago
How do you implement this kind of thing in an FPGA ? It sounds intriguing.

nvader 12y ago

> If the device fails, you have exceeded the ragings. Minor typo, or anachronistic use of early 21st Century slang that suggests time traveller activity?

danjayh 12y ago

Reminds me of the retro encabulator (which was actually a video, not a data sheet) https://www.youtube.com/watch?v=NpnEiOOfu1Q https://www.youtube.com/watch?v=NpnEiOOfu1Q "The line-up consisted simply of six hydrocoptic marzul vanes so fitted to the ambaphascient lunar wain shaft that side fumbling was effectively prevented." Ahhh, classic.

JonnieCache 12y ago
https://www.youtube.com/watch?v=noSOFIJdfwM https://www.youtube.com/watch?v=noSOFIJdfwM

robert_tweed 12y ago

Perhaps not write-only memory per se, but write-only registers are a pretty common thing if you do any hardware-level programming. Though admittedly this isn't something I've done for a number of years, IIRC both the VGA and the original Sound Blaster had write-only registers which you would use to request some change in state, and some other registers that would reflect the actual current state of the device if/when the request was honoured. Of course these are not write-only in the sense that nothing can read their contents, since they are provided as an interface to some coprocessor like a GPU or a sound chip. That coprocessor can of course read the incoming data. They are more like the hardware equivalent of mutator methods on top of private properties.