Here's how that would look in the instruction set we use here ($100M commercial product) ; ARM spells it ADD R0, R1, R2, LSL #8 ; We spell it

Here's how that would look in the instruction set we use here ($100M commercial product) ; ARM spells it ADD R0, R1, R2, LSL #8 ; We spell it CLX R0 ; 1 cycles ADX R1 ; 1 ADX R2 ; 1 LDX N, 8 ; 3 RSX ; N (const 8 in this case) Try optimizing THAT!