6 ms·

Update on STM

• kazagistar 13y ago
  Is there any plans to work hardware transactional memory into the mix?
  • kingkilr 13y ago
    Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
    • 4buser 13y ago
      Even new Intel Haswell's STM?
      • sanxiyn 13y ago
        Yes, Intel TSX too has a limited transaction size.
• deleted 13y ago
  [deleted]
• nn4 13y ago
  Obligatory anti STM hype links: http://queue.acm.org/detail.cfm?id=1454466 http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_jucksJ:www.bluebytesoftware.com/blog/2010/01/03/ABriefRetrospectiveOnTransactionalMemory.aspx+&cd=1&hl=en&ct=clnk&gl=us http://webcache.googleusercontent.com/search?q=cache:HhZcU_j... Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.