5 ms·

Looks like you know some internal details of the A53 cores, can you share the source?

• phire 9d ago
  The fact it does speculative execution and dual-issue is well documented. The chipsandcheese article [0] is probably the best overview. The "how" it does dual-issue is not documented at all, so I'm speculating. There is no smoking gun saying "register renaming". While it would be possible to implement its known capabilities without any kind of renaming, it would be so much simpler to implement it with register renaming. The thing is.. once your forwarding network and hazard detection gets complicated enough, it basically becomes a janky form of register renaming. So it's cleaner to just implement proper register renaming, and actually saves hardware. While the A53 might issue in-order, the pipelines have different lengths and they don't finish executing in order. I find the fact the A53 can speculate a few instructions past a cache miss to be very interesting, along with the fact it can issue two writes to the same logical register in a single cycle. Also, the smoking gun is that the A510 (same lineage as the A53) is documented to do out-of-order issue (see chipsandcheese again [1]), so it must be doing register renaming. ARM still insist on still calling it an in-order core because it's OoO is so much more limited to modern OoO cores, but it's more OoO than early PowerPC designs (including the G3) that everyone is happy applying the OoO label to. [0] https://chipsandcheese.com/p/arms-cortex-a53-tiny-but-important https://chipsandcheese.com/p/arms-cortex-a53-tiny-but-import... [1] https://chipsandcheese.com/p/arms-cortex-a510-two-kids-in-a-trench-coat https://chipsandcheese.com/p/arms-cortex-a510-two-kids-in-a-...