I looked at the linked repo at https://github.com/machdyne/zeitlos/tree/main https://github.com/machdyne/zeitlos/tree/main, just skimmed a few of the Verilog HD

I looked at the linked repo at https://github.com/machdyne/zeitlos/tree/main https://github.com/machdyne/zeitlos/tree/main, just skimmed a few of the Verilog HDL files and C program files. There is a ton of work here! The files are rich with block comments that explain design decisions, and what's going on.