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Yes, but compared to RISC-V neither OpenSPARC nor OpenPOWER are really going anywhere. Not really sure why, maybe the lawyers read the fine print about the leve
by jabl 1mo ago
Yes, but compared to RISC-V neither OpenSPARC nor OpenPOWER are really going anywhere. Not really sure why, maybe the lawyers read the fine print about the level of openness they actually provide and decide that nope, not gonna touch that one?
Technically just looking at the ISA both SPARC and POWER seem fine enough. So why is nobody interested?
(Talos is interesting but not really an answer to the question, as it seems to be focused on building affordable-ish systems around an existing CPU, not developing new CPU's.)
- Conan_Kudo 1mo agoOpenSPARC is under the GPL, which is probably why it didn't go anywhere directly. OpenPOWER is under permissive creative commons licenses, and people are iterating on the open source cores released by them. But the arrangement with efabless didn't go anywhere, and the company shut down last year without warning. So there's nowhere to experiment with producing chips.
- initramfs 1mo agohttps://wafer.space https://wafer.space allows chips but I think tinytapeout became what efabless was doing: https://chipfoundry.io/ https://chipfoundry.io/ Also Hitachi's SH-2 & SH-4 patents expired in 2016, so J-core picked up where they left off: https://j-core.org/ https://j-core.org/ MIPS also went open source around 2018: https://www.datacenterknowledge.com/data-center-hardware/mips-joins-risc-v-as-second-open-source-alternative-to-arm https://www.datacenterknowledge.com/data-center-hardware/mip...
- Conan_Kudo 26d agoThe "MIPS Open" program never launched. MIPS itself eventually pivoted to RISC-V, and is now owned by Globalfoundries. I don't think the j-core effort is still active? It would be interesting to see it continue, though.