> I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementation

> I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? Yes, the fundamental problem is the fact that everybody involved in RISC-V wants to sell IP instead of a chip. The problem with the RISC-V chips in non-embedded contexts (ie desktop or server) has absolutely nothing to do with the instruction set architecture (not entirely true but a really good first approximation). The problem is that performance is strongly dependent upon your high speed interfaces--memory, graphics, PCI, etc. And those blocks need to be strongly integrated in with your CPU interfaces. However, if you buy a whole bunch of IP blocks and then just wire them together, your performance is going to be sub-par. And this is what every single RISC-V chip that I know of currently is. It's not beyond someone to sit down and do the required integration like Apple did for ARM. There's just insufficient money in it so nobody is going to expend the engineers.