Yeah, I'm dubious of the "3x wafers" claim, but I heard "3x wafer capacity", which sounds more logical. More steps per wafer (for TSVs) -> more time spent in th

Yeah, I'm dubious of the "3x wafers" claim, but I heard "3x wafer capacity", which sounds more logical. More steps per wafer (for TSVs) -> more time spent in the fan per wafer & machines busy with HBM wafer -> smaller wafer / chip output.