5 ms·

Just to be clear, I made a working prototype (and put a hyperbole in the title), I have a lot to learn still. You can learn something practical like "embedded

Just to be clear, I made a working prototype (and put a hyperbole in the title), I have a lot to learn still. You can learn something practical like "embedded DisplayPort should be impedance controlled to 100 Ohms" without fully understanding the physics behind it. AI can be very convincing. It told me to put the ESD protection as close the Ethernet connector as possible, so I put it between the port and the magnetics. This worked, but resulted in around 1% packet loss. When I moved it after the magnetics, I got 0% packet loss. This cost me a full revision, but I'd say this is the price to pay for not learning everything by the book.

15155 2mo ago
> so I put it between the port and the magnetics For GP: this is something you would learn from a PHY manufacturer's EVK schematics and layouts. TI (especially), NXP, Microchip show correct magnetics/ESD part numbers and placement - the trickier thing here is finding an EVK that doesn't just use an integrated MagJack. See https://www.ti.com/lit/df/snlr034/snlr034.pdf https://www.ti.com/lit/df/snlr034/snlr034.pdf
- matheusmoreira 2mo ago
  Yeah I'm relying a lot on the TI datasheets for "known good" power supply schematics. I chose an Intel N100 SoM and there's an example carrier board, but the whole point of my project is to customize that board. I wanted to do things like rewire the HSIO lines: turn the GPU PCIe socket into extra USB 3.0 ports and M.2 E sockets. The "known good" designs won't port over cleanly. It's PCIe gen3 over short runs, Claude tells me it's "forgiving" but I'm still nervous about it. I'm placing an Intel I210-IT onto this board too, would definitely appreciate any tips!!