DRAM hit a barrier at 10 nm a few years ago[0], so 16 nm is actually even closer to state-of-the-art. E.g. Micron newest node (1-γ) is their sixth at 10 nm [1]

DRAM hit a barrier at 10 nm a few years ago[0], so 16 nm is actually even closer to state-of-the-art. E.g. Micron newest node (1-γ) is their sixth at 10 nm [1] and their first EUV-based node. The problem is that DRAM is fundamentally based on storing charge in a capacitor and how much charge a capacitor can store is a result of the geometry of the capacitor. So either someone will have to figure out a way to make the same size capacitor take up less space on the RAM chip (this is what broke the previous 20 nm barrier) or someone will have to invent a practical way of making RAM with less than 1 capacitor per bit. 0: https://semiengineering.com/dram-scaling-challenges-grow/ https://semiengineering.com/dram-scaling-challenges-grow/ 1: https://www.techpowerup.com/333111/micron-announces-shipment-of-1g-1-gamma-dram-companys-first-euv-memory-node https://www.techpowerup.com/333111/micron-announces-shipment...