6 ms·
Indeed!! MIPS - $zero RISC-V - x0 SPARC - %g0 ARM64 - XZR
by lynguist 5mo ago
Indeed!!
MIPS - $zero
RISC-V - x0
SPARC - %g0
ARM64 - XZR
- classichasclass 5mo agoPowerPC: "r0 occasionally" (with certain instructions like addi, though this might be better considered an edge case of encoding)
- matja 5mo agoAlpha: r31, f31
- Findecanor 5mo agoOn 64-bit ARM, the same register number is XZR in some instructions and the stack pointer in others.