5 ms·
What's not guaranteed for "normal" loads and stores on many architectures is the order in which writes become visible to other CPU cores.
by pjdesno 6mo ago
What's not guaranteed for "normal" loads and stores on many architectures is the order in which writes become visible to other CPU cores.
- wat10000 6mo agoRight, that's what the various memory ordering constants are for in C++ atomics, and other languages will likely have an equivalent. On such architectures, those will emit special instructions or barriers.