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Bigger chip = more surface area = higher chance for somewhere in the chip to have a manufacturing defect Yields on silicon are great, but not perfect

by DocJade 7mo ago

moralestapia 7mo ago
Does that mean smaller chips are made from smaller wafers?
- Sohcahtoa82 7mo ago
  Nope. They use the same size wafers and then just put more chips on a wafer.
  - moralestapia 7mo ago
    So, does a wafer with a huge chip has more defects per area than a wafer with 100s of small chips?
    - dgfl 7mo ago
      There’s an expected amount of defects per wafer. If a chip has a defect, then it is lost (simplification). A wafer with 100 chips may lose 10 to defects, giving a yield of 90%. The same wafer but with 1000 smaller chips would still have lost only 10 of them, giving 99% yield.
      - moralestapia 7mo ago
        As another comment referenced in this thread states, Cerebras seems to have solved by making their big chip a lot of much smaller cores that can be disposed of if they have errors.
        dgfl 7mo ago
        Indeed, the original comment you replied to actually made no sense in this case. But there seemed to be some confusion in the thread, so I tried to clear that up. I hope I’ll get to talk with one of the cerebras engineers one day, that chip is really one of a kind.
        moralestapia 7mo ago
        Yes, amazing tech. You should join their Discord, it's pretty active these days!
- wat10000 7mo ago
  They can be made from large wafers. A defect typically breaks whatever chip it's on, so one defect on a large wafer filled with many small chips will still just break one chip of the many on the wafer. If your chips are bigger, one defect still takes out a chip, but now you've lost more of the wafer area because the chip is bigger. So you get a super-linear scaling of loss from defects as the chips get bigger. With careful design, you can tolerate some defects. A multi-core CPU might have the ability to disable a core that's affected by a defect, and then it can be sold as a different SKU with a lower core count. Cerebras uses an extreme version of this, where the wafer is divided up into about a million cores, and a routing system that can bypass defective cores. They have a nice article about it here: https://www.cerebras.ai/blog/100x-defect-tolerance-how-cerebras-solved-the-yield-problem https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb...

Bigger chip = more surface area = higher chance for somewhere in the chip to have a manufacturing defect Yields on silicon are great, but not perfect

by DocJade 7mo ago

Bigger chip = more surface area = higher chance for somewhere in the chip to have a manufacturing defect Yields on silicon are great, but not perfect

moralestapia 7mo ago

Does that mean smaller chips are made from smaller wafers?

Sohcahtoa82 7mo ago
Nope. They use the same size wafers and then just put more chips on a wafer.
- moralestapia 7mo ago
  So, does a wafer with a huge chip has more defects per area than a wafer with 100s of small chips?
  - dgfl 7mo ago
    There’s an expected amount of defects per wafer. If a chip has a defect, then it is lost (simplification). A wafer with 100 chips may lose 10 to defects, giving a yield of 90%. The same wafer but with 1000 smaller chips would still have lost only 10 of them, giving 99% yield.
    - moralestapia 7mo ago
      As another comment referenced in this thread states, Cerebras seems to have solved by making their big chip a lot of much smaller cores that can be disposed of if they have errors.
      - dgfl 7mo ago
        Indeed, the original comment you replied to actually made no sense in this case. But there seemed to be some confusion in the thread, so I tried to clear that up. I hope I’ll get to talk with one of the cerebras engineers one day, that chip is really one of a kind.
        moralestapia 7mo ago
        Yes, amazing tech. You should join their Discord, it's pretty active these days!
wat10000 7mo ago
They can be made from large wafers. A defect typically breaks whatever chip it's on, so one defect on a large wafer filled with many small chips will still just break one chip of the many on the wafer. If your chips are bigger, one defect still takes out a chip, but now you've lost more of the wafer area because the chip is bigger. So you get a super-linear scaling of loss from defects as the chips get bigger. With careful design, you can tolerate some defects. A multi-core CPU might have the ability to disable a core that's affected by a defect, and then it can be sold as a different SKU with a lower core count. Cerebras uses an extreme version of this, where the wafer is divided up into about a million cores, and a routing system that can bypass defective cores. They have a nice article about it here: https://www.cerebras.ai/blog/100x-defect-tolerance-how-cerebras-solved-the-yield-problem https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb...