17 ms·

Need chip art / logo for free and open source silicon clone of Z80 CPU

3 points by __rej__ 9mo ago

__rej__ 9mo ago
I am working on a Z80 replica in 180 nm and would love some ideas and sketches for the Free and Open Source Silicon (FOSSi) Z80 logo - to "bake" it directly into the silicon on the chip! Here are some cool examples of the chip art: https://hackaday.io/page/11717-chip-graffiti-hilarious-arts-of-integrated-circuits https://hackaday.io/page/11717-chip-graffiti-hilarious-arts-... This Z80 replica will be manufactured with the new https://wafer.space https://wafer.space service.
- java-man 9mo ago
  Is it possible to place some low power SRAM and flash/EEPROM on the same die as well?
  - __rej__ 9mo ago
    It is a very good idea about SRAM! Around 16KB of SRAM can fit on the die (Wafer.Space provides 20 mm^2 area per chip) - that could be useful for both fixing old computers like ZX Spectrum and handy for turning Z80 into a tiny MCU. However Flash/EEPROM is currently out of the question. I don't know of any open-source versions available. That would have been a very serious undertaking on it's own!
    - java-man 9mo ago
      Maybe 64k or even more with 2-transistor SRAM cells like those described in https://ieeexplore.ieee.org/document/8993520 https://ieeexplore.ieee.org/document/8993520 ?
WorldPeas 9mo ago
thoughts? I could send the SVG as well. Not exactly cool but I thought it would be a nice homage (I acknowledge I relinquish the copyright to you etcetc) https://0x0.st/PrQf.png https://0x0.st/PrQf.png
- __rej__ 9mo ago
  I like it! What about also "XORing" 80 somewhere on the bottom part of Z letter? Would you mind submitting a ticket "issue" with it please?: https://github.com/rejunity/z80-open-silicon/issues https://github.com/rejunity/z80-open-silicon/issues PS: both PNG and SVG would be handy.
  - WorldPeas 9mo ago
    no prob!
__rej__ 9mo ago
FYI this how chip looks right now in the 5 mm^2 configuration. https://github.com/rejunity/z80-open-silicon/blob/main/docs/ws0_z80_wip.png https://github.com/rejunity/z80-open-silicon/blob/main/docs/... The colourful lines in the middle are the metal wires (layers 2,3 & 4) displaying the interconnect inside the chip and connections to the I/O pads which in turn will be wirebonded to the external pins.

3 points by __rej__ 9mo ago

I am working on a Z80 replica in 180 nm and would love some ideas and sketches for the Free and Open Source Silicon (FOSSi) Z80 logo - to "bake" it directly into the silicon on the chip! Here are some cool examples of the chip art: https://hackaday.io/page/11717-chip-graffiti-hilarious-arts-of-integrated-circuits https://hackaday.io/page/11717-chip-graffiti-hilarious-arts-... This Z80 replica will be manufactured with the new https://wafer.space https://wafer.space service.

java-man 9mo ago
Is it possible to place some low power SRAM and flash/EEPROM on the same die as well?
- __rej__ 9mo ago
  It is a very good idea about SRAM! Around 16KB of SRAM can fit on the die (Wafer.Space provides 20 mm^2 area per chip) - that could be useful for both fixing old computers like ZX Spectrum and handy for turning Z80 into a tiny MCU. However Flash/EEPROM is currently out of the question. I don't know of any open-source versions available. That would have been a very serious undertaking on it's own!
  - java-man 9mo ago
    Maybe 64k or even more with 2-transistor SRAM cells like those described in https://ieeexplore.ieee.org/document/8993520 https://ieeexplore.ieee.org/document/8993520 ?

WorldPeas 9mo ago

thoughts? I could send the SVG as well. Not exactly cool but I thought it would be a nice homage (I acknowledge I relinquish the copyright to you etcetc) https://0x0.st/PrQf.png https://0x0.st/PrQf.png

__rej__ 9mo ago
I like it! What about also "XORing" 80 somewhere on the bottom part of Z letter? Would you mind submitting a ticket "issue" with it please?: https://github.com/rejunity/z80-open-silicon/issues https://github.com/rejunity/z80-open-silicon/issues PS: both PNG and SVG would be handy.
- WorldPeas 9mo ago
  no prob!

__rej__ 9mo ago

FYI this how chip looks right now in the 5 mm^2 configuration. https://github.com/rejunity/z80-open-silicon/blob/main/docs/ws0_z80_wip.png https://github.com/rejunity/z80-open-silicon/blob/main/docs/... The colourful lines in the middle are the metal wires (layers 2,3 & 4) displaying the interconnect inside the chip and connections to the I/O pads which in turn will be wirebonded to the external pins.