7 ms·

If I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don'

by huyage 11mo ago

If I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don't really need the out-of-order execution. I also want to be able to run it on a cheap FPGA, something like Artix A7.

daedalus- 11mo ago
Try neorv32: https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32
- huyage 11mo ago
  Thanks. Looks good! Are you aware of any 64-bit options?
- jhallenworld 11mo ago
  Wish it was Verilog or SystemVerilog..
rwmj 11mo ago
Rocket-chip is widely used (https://github.com/chipsalliance/rocket-chip https://github.com/chipsalliance/rocket-chip). It can fit on smaller FPGAs. If you want something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 (https://github.com/YosysHQ/picorv32 https://github.com/YosysHQ/picorv32).
dmitrygr 11mo ago
https://github.com/Wren6991/Hazard3 https://github.com/Wren6991/Hazard3 this one is well tested in real life and works well (it is the RV core in RP2350)
panick21 11mo ago
This is what the OpenHW Foundaiton is for. Providing well verified cores for people who just need a core. They are based on the original Pulp Cores from the ETH Zürich and Unviersity of Bolongia. See: https://openhwfoundation.org/ https://openhwfoundation.org/ Or because its part of OpenTitan, Ibex sees a lot of development: https://github.com/lowRISC/ibex https://github.com/lowRISC/ibex
drob518 11mo ago
There’s a nice list of open source cores here: https://github.com/suryakantamangaraj/AwesomeRISC-VResources https://github.com/suryakantamangaraj/AwesomeRISC-VResources
kragen 11mo ago
Claire Wolf's PicoRV32 seems to get a lot of "simple and synthesizable RISC-V design to run on a cheap FPGA" use, although that's more typically for much cheaper FPGA's than an Artix A7, like an iCE40. SeRV is even cheaper and simpler but much slower. Graeme Smecher’s RVC-first "Minimax" is almost as simple as SeRV but not nearly as slow. I haven't tried any of them, though, so take this with a Himalayan salt lamp.
- jhallenworld 11mo ago
  I've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf. I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.

by huyage 11mo ago

daedalus- 11mo ago

Try neorv32: https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32

huyage 11mo ago
Thanks. Looks good! Are you aware of any 64-bit options?
jhallenworld 11mo ago
Wish it was Verilog or SystemVerilog..

rwmj 11mo ago

Rocket-chip is widely used (https://github.com/chipsalliance/rocket-chip https://github.com/chipsalliance/rocket-chip). It can fit on smaller FPGAs. If you want something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 (https://github.com/YosysHQ/picorv32 https://github.com/YosysHQ/picorv32).

dmitrygr 11mo ago

https://github.com/Wren6991/Hazard3 https://github.com/Wren6991/Hazard3 this one is well tested in real life and works well (it is the RV core in RP2350)

panick21 11mo ago

This is what the OpenHW Foundaiton is for. Providing well verified cores for people who just need a core. They are based on the original Pulp Cores from the ETH Zürich and Unviersity of Bolongia. See: https://openhwfoundation.org/ https://openhwfoundation.org/ Or because its part of OpenTitan, Ibex sees a lot of development: https://github.com/lowRISC/ibex https://github.com/lowRISC/ibex

drob518 11mo ago

There’s a nice list of open source cores here: https://github.com/suryakantamangaraj/AwesomeRISC-VResources https://github.com/suryakantamangaraj/AwesomeRISC-VResources

kragen 11mo ago

Claire Wolf's PicoRV32 seems to get a lot of "simple and synthesizable RISC-V design to run on a cheap FPGA" use, although that's more typically for much cheaper FPGA's than an Artix A7, like an iCE40. SeRV is even cheaper and simpler but much slower. Graeme Smecher’s RVC-first "Minimax" is almost as simple as SeRV but not nearly as slow. I haven't tried any of them, though, so take this with a Himalayan salt lamp.

jhallenworld 11mo ago
I've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf. I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.