I checked Godbolt, with RISC-V instead of ARM since I'm more familiar with that, and it doesn't look like it. https://gcc.godbolt.org/z/b5s4WjnTG https://gcc.g

I checked Godbolt, with RISC-V instead of ARM since I'm more familiar with that, and it doesn't look like it. https://gcc.godbolt.org/z/b5s4WjnTG https://gcc.godbolt.org/z/b5s4WjnTG (amomax is the atomic fetch-max instruction. lr and sc are load-reserved and store-conditional instructions; sc is like a regular store except it only succeeds if the address was not modified since the previous lr that accessed it. IOW the assembly is basically one-to-one with the C source.)