Interesting, going through the comments… “WiFi is still via SDIO on the Broadcom chip, IIRC.” <https://www.jeffgeerling.com/comment/34061#comment-34061 https:

Interesting, going through the comments… “WiFi is still via SDIO on the Broadcom chip, IIRC.” <https://www.jeffgeerling.com/comment/34061#comment-34061 https://www.jeffgeerling.com/comment/34061#comment-34061> And “Ran a quick search on Raspberry Pi's github linux repo and found where I got my info from re the stuff they took out on D0. From what I can see, they actually removed device tree support for parts of the chip they don't use on C0/C1 that are not present on D0, and folded these changes into the same DTS file. They also seem to have added a DTS specifically for the D0 stepping, which seems to be register changes, i.e. stuff that is present in both variants of the chip but has moved or needs to otherwise be handled differently between C1 and D0. See https://github.com/raspberrypi/linux/pull/5847 https://github.com/raspberrypi/linux/pull/5847, specifically for the bits removed see <https://github.com/raspberrypi/linux/pull/5847/commits/8be0890e7464324e66c2821989352f01b412aae0 https://github.com/raspberrypi/linux/pull/5847/commits/8be08...>“ <https://www.jeffgeerling.com/comment/34061#comment-34061 https://www.jeffgeerling.com/comment/34061#comment-34061> Something broke. Without going through the obsd code it remains unknown. Unless there is reference to uart3 & uart4?