Oh boy, I definitely considered that — turning PyXL into a RISC-V extension was an early idea I thought of. It could probably be adapted into one. But I ultim

Oh boy, I definitely considered that — turning PyXL into a RISC-V extension was an early idea I thought of. It could probably be adapted into one. But I ultimately decided to build it as its own clean design because I wanted the flexibility to rethink the entire execution model for Python — not just adapt an existing register-based architecture. FPGA is for prototyping. although this could probably be used as a soft core. But looking forward, ASIC is definitely the way to go.