DDR5 doesn't have an In-Band ECC. What they have is On-Die ECC, and is not visible to the memory controller (i.e. error information won't be reported by EDAC),

DDR5 doesn't have an In-Band ECC. What they have is On-Die ECC, and is not visible to the memory controller (i.e. error information won't be reported by EDAC), and only corrects 1-bit when they're stored/retrieved, where Side-Band ECC (regular ECC) and In-Band ECC can correct 1-bit and detect 2-bits, and can also correct/detect memory corruption during transit.