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Thank you for your work, every article brightens my day! Every time I look at the chips from 70s and 80s, I notice how huge the features are. Was that determi

Thank you for your work, every article brightens my day! Every time I look at the chips from 70s and 80s, I notice how huge the features are. Was that determined by the current stepper technology at the time, or by the fact that people drew the early designs by hand? Or am I totally wrong and the chips are always at the limit of the contemporary technology?

kens 2y ago
The feature size on chips has steadily shrunk from 10 µm for the Intel 8008 to a few nanometers nowadays. The feature size is determined by the limits of contemporary technology, which steadily improves as described by Moore's Law. Many different technological aspects need to improve to shrink the features, from the design techniques to the optics to the chemical processes.
- Pet_Ant 2y ago
  10 is 10,000 nm. "3nm" apparently has a "gate pitch" of 48 nm, that is 0.5% of the size! I don't know that "gate pitch" is the correct metric, but I do know that modern marketing nodes don't correspond to reality so this is my crude attempt at trying to bring it to physical reality. Not sure if I did it correctly.
bobmcnamara 2y ago
> Or am I totally wrong and the chips are always at the limit of the contemporary technology? I can chime in here. There are many things that determine the feature size. There is the process limit, yes, and if your needs are simple digital logic, that's often going to be the density limit. But if you need NOR flash, there's a stability limit around 40nm process node. You can use smaller transistors for everything else, but soon the NOR is most of the chip. But what if you need a 1 Amp FET in your PMIC? Well, that won't shrink with process node at all, so maybe a cheaper process node is better to use. It really depends.
- java-man 2y ago
  Yes, I was referring to 70's and 80's. Even today, I think, there are applications where 150 nm process is perfectly fine - RFID, transportation cards etc. If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs, so it is expected. When did transition from hand-drawn to computer-generated designs happen?
  - greenyoda 2y ago
    > If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs... TTL wasn't the first attempt at ICs. Before TTL, there was RTL: https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_logic https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_lo...
  - bonzini 2y ago
    Around the mid 80s, for example the 386 was the first x86 processor to largely use standard cells. It seems appropriate to cite Ken's blog post on the topic: https://www.righto.com/2024/01/intel-386-standard-cells.html https://www.righto.com/2024/01/intel-386-standard-cells.html
- CamperBob2 2y ago
  But what if you need a 1 Amp FET in your PMIC? You use lots of very small FETs in parallel (and derate the living bejesus out of the SOA curves, because there's no chance that they'll all run at the same temperature.)
  - kragen 2y ago
    i mean in effect a hexfet is a lot of very small fets in parallel nice thing about fets, hotspots don't hog current, so you don't have to derate the living bejesus out of the soa curves
    - CamperBob2 2y ago

kens 2y ago

The feature size on chips has steadily shrunk from 10 µm for the Intel 8008 to a few nanometers nowadays. The feature size is determined by the limits of contemporary technology, which steadily improves as described by Moore's Law. Many different technological aspects need to improve to shrink the features, from the design techniques to the optics to the chemical processes.

Pet_Ant 2y ago
10 is 10,000 nm. "3nm" apparently has a "gate pitch" of 48 nm, that is 0.5% of the size! I don't know that "gate pitch" is the correct metric, but I do know that modern marketing nodes don't correspond to reality so this is my crude attempt at trying to bring it to physical reality. Not sure if I did it correctly.

bobmcnamara 2y ago

> Or am I totally wrong and the chips are always at the limit of the contemporary technology? I can chime in here. There are many things that determine the feature size. There is the process limit, yes, and if your needs are simple digital logic, that's often going to be the density limit. But if you need NOR flash, there's a stability limit around 40nm process node. You can use smaller transistors for everything else, but soon the NOR is most of the chip. But what if you need a 1 Amp FET in your PMIC? Well, that won't shrink with process node at all, so maybe a cheaper process node is better to use. It really depends.

java-man 2y ago
Yes, I was referring to 70's and 80's. Even today, I think, there are applications where 150 nm process is perfectly fine - RFID, transportation cards etc. If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs, so it is expected. When did transition from hand-drawn to computer-generated designs happen?
- greenyoda 2y ago
  > If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs... TTL wasn't the first attempt at ICs. Before TTL, there was RTL: https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_logic https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_lo...
- bonzini 2y ago
  Around the mid 80s, for example the 386 was the first x86 processor to largely use standard cells. It seems appropriate to cite Ken's blog post on the topic: https://www.righto.com/2024/01/intel-386-standard-cells.html https://www.righto.com/2024/01/intel-386-standard-cells.html
CamperBob2 2y ago
But what if you need a 1 Amp FET in your PMIC? You use lots of very small FETs in parallel (and derate the living bejesus out of the SOA curves, because there's no chance that they'll all run at the same temperature.)
- kragen 2y ago
  i mean in effect a hexfet is a lot of very small fets in parallel nice thing about fets, hotspots don't hog current, so you don't have to derate the living bejesus out of the soa curves
  - CamperBob2 2y ago