5 ms·
HBM is slower than DDR per pin, the speed gain is from a hugely parallel bus. Parallel means latency if you have non "embarrassingly parallelizable" tasks?
by spintin 2y ago
HBM is slower than DDR per pin, the speed gain is from a hugely parallel bus.
Parallel means latency if you have non "embarrassingly parallelizable" tasks?
- Tuna-Fish 2y agoThe smallest transfer done from memory is a single cache line, which on most desktop machines is 64 bytes, or 512 bits. You could imagine a memory bus that was 512 bits wide and transferred a cache line per clock, and this would improve latency when compared to a serial bus with higher clock speed. HBM doesn't do that, though, instead every HBM3 module has 16 individual 64-bit channels, with 8n prefetch (that is, when you send a single request to a single channel, it will respond with 512 bits over 8 cycles).
- dist-epoch 2y agoDDR5 has 2 independent 32-bit lanes. Multiple transfers are required for 64 bytes.
- Tuna-Fish 2y agoDDR5 has a 16n prefetch, so a single transfer from a 32-wide channel moves 64 bytes.