Hardware implementation in synthesisable Verilog RTL. Synthesises to about 700+ slices at 150MHz on a Spartan6. https://github.com/sybreon/dcpu16 https://gith

Hardware implementation in synthesisable Verilog RTL. Synthesises to about 700+ slices at 150MHz on a Spartan6. https://github.com/sybreon/dcpu16 https://github.com/sybreon/dcpu16