The addressing modes do exist on 68020+ (https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf https://www.nxp.com/files-static/archives/doc/re

The addressing modes do exist on 68020+ (https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf https://www.nxp.com/files-static/archives/doc/ref_manual/M68... section 2.2), but I don't think any compiler will generate them (even with -mcpu=68020) as I think they're not actually faster than doing it the normal way (even if that costs a register), maybe slower, but I'd have to check the cycle counts. EDIT: Yeah, so if I'm not misreading MC68020UM the memory indirect mode is slower move.l #3,([6,a0,d0.l*8],4) ; 9 cycles best case vs. move.l 6(a0,d0.l*8),a0 ;4 move.l #3,4(a0) ; 3