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(some rambling questions here that are only semi-related:) NASA is really anal about radiation concerns, insisting the caches have ECC (or they run it with cac

(some rambling questions here that are only semi-related:) NASA is really anal about radiation concerns, insisting the caches have ECC (or they run it with cache disabled). For the instruction cache this makes sense (as well as any higher caches that would store instructions). With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger).

toast0 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Maybe? But CPU cost basically doesn't matter compared to launch cost. Power budget given the required computing needs during critical sections of the mission is probably the biggest priority after reliability. Modern cpus are good at compute/watt, but not necessarily at low watts at low load. No idea re: feature size, for cosmic rays and dram, it was thought that shrinking beyond some point was going to increase failures dramatically, but then it was fine. But in space radiation is more than cosmic rays.
shagie 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Power constraints and heat dissipation constraints. https://arstechnica.com/science/2019/11/space-grade-cpus-how-do-you-send-more-computing-power-into-space/3/ https://arstechnica.com/science/2019/11/space-grade-cpus-how... > BAE RAD5545 is probably the most powerful radiation-hardened processor available today. Fabricated in the 45nm process, it is a 64-bit quad-core machine clocked at 466MHz with power dissipation of up to 20 Watts—and 20 Watts is a lot. A Quad Core i5 sitting in a 13-inch MacBook Pro 2018 is a 28 Watt processor. It can heat its thin aluminum chassis to really high temperatures up to a point where it becomes an issue for some users. Under more computationally intensive workloads, fans immediately kick in to cool the whole thing down. The only issue is that, in space, fans would do absolutely nothing, because there is no air they could blow onto a hot chip. The only possible way to get heat out of a spacecraft is through radiation, and that takes time. Sure, heat pipes are there to take excessive heat away from the processor, but this heat has to eventually go somewhere. Moreover, some missions have tight energy budgets, and they simply can’t use powerful processors like RAD5545 under such restrictions. That’s why the European GR740 has power dissipation at only 1.5 Watts. It’s not the fastest of the lot, but it is the most efficient. It simply gives you the most computational bang per Watt. The HPSC with 10 Watt power dissipation comes in at a close second, but not always.
- nynx 4y ago
  45nm is massive for a high-performance processor. Rad-hardening compute is frankly overrated. Have multiple and compare state at a high-rate.
  - shagie 4y ago
    But you can't power multiple on the energy budget that you've got. Perseverance is running on 110 watts ( https://mars.nasa.gov/mars2020/spacecraft/rover/electrical-power/ https://mars.nasa.gov/mars2020/spacecraft/rover/electrical-p... ). The RAD5545 uses 20 watts of that budget. Tripling it means it doesn't have enough energy to power the rest of the rover. The Mars MAVEN ( https://spaceflight101.com/maven/spacecraft-information/ https://spaceflight101.com/maven/spacecraft-information/ ) is using a RAD-750 which uses 10 watts of power ( https://en.wikipedia.org/wiki/RAD750 https://en.wikipedia.org/wiki/RAD750 ) (also used in the JWST). The RAD-750... > The processor can endure radiation doses that are a million times more extreme than what is considered fatal to humans. And while you may argue "yes, that seems a bit excessive" - the goal isn't "it can run in those extremes" but rather... > Also, RAD750 will not suffer more than one event requiring interventions from Earth over a 15-year period. > “The RAD750 card is designed to accommodate all those single event effects and survive them. The ultimate goal is one upset is allowed in 15 years. An upset means an intervention from Earth — one ‘blue screen of death’ in 15 years. We typically have contracts that (specify) that,” said Vic Scuderi BAE Business Manager. ... because it can't be replaced easily. From Wikipedia: > The CPU can withstand an absorbed radiation dose of 2,000 to 10,000 grays
    - incrudible 4y ago
      I do not buy the power argument. A modern chip is orders of magnitude more power efficient, especially at low voltage. You could easily have multiples of these within the same power budget.
      - ilyt 4y ago
        But smaller size increases the chance for event (which might be compensated) but also increases chance for fatal damage to happen. The radiation in space is not dangerous because it just produces a bit of current that can flip a bit; it is dangerous because it is strong enough to bump a bunch out of their position in silicon crystal, causing permanent damage that will accumulate over time. And when your feature size is starting to measure in <100 atoms it would be easy for single high energy event to break whole core.
LargeTomato 4y ago
>With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Nasa needs redundancy. Say we ran a program in triplicate, one on each core, and compared the outputs. We still don't have redundancy here because the chip can still fail in a way that will cause problems for all three cores. >My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger). Larger gates tend to be more resilient to radiation. I don't know exactly why. The fabrication tech is also important. Some types of chip manufacturing processes results in more resilient chips. I'm sorry but I don't know enough about it to elaborate further.
- afiori 4y ago
  Not an expert but essentially radiations can produce electrons in random places flipping one or more transistors unexpectedly. Larger transistors need more electrons so they are slightly more resistant.
  - denton-scratch 4y ago
    Because larger transistors need more electrons, they also need more power to switch. I guess that circuitry made from valves/vacuum tubes might provide high radiation resistance?
    - ilyt 4y ago
      I mean, you could just use big transistors
  - geomark 4y ago
    That's single event upset (SEU). The other radiation issue is total dose. That's when charge gradually builds up in insulating gates due to ionizing radiation. It's permanent, and eventually reaches the point that the transistor is always on so has a permanent fault. One of the factors is collection area, so larger gates are not less susceptible because they have a larger collection area. But if they run at a higher voltage that can make them more tolerant to total dose.
numpad0 4y ago
> couldn't NASA use these for redundancy? > how much more resilient are older processes with larger feature size compared to modern 6/7nm ? If I may paraphrase your questions, I think you are trying to ask "isn't rad hardening a bit overrated? are space chips that good?" - and a Wikipedia edit[1] that has kept most of its original form for more than 15 years have been answering that question thanklessly: > Hardened chips are often manufactured on insulating substrates instead of the usual semiconductor wafers. Silicon oxide (SOI) and sapphire (SOS) are commonly used. While vanilla chips can withstand between 5 and 10 krad, SOI and SOS can survive doses many orders of magnitude greater. So the answer is, if 10krad(in lifetime) and [unspecified] events/seconds is enough for your requirements, maybe you don't need rad-hard chips. If your requirements are going to be magnitude grater(you can math it from data), then you might want it, and yes, there are differences in orders of magnitudes. 1: https://en.wikipedia.org/w/index.php?title=Radiation_hardening&oldid=46164991 https://en.wikipedia.org/w/index.php?title=Radiation_hardeni...
ilyt 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Think shuttle had 3 separate computers running same code and having mechanism to vote out the one giving bad output ? There are also some automotive ARMs that are basically 2 cores shifted physically 90 degrees running lockstep and some logic to reset if they disagree > My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger). I'd imagine by a lot. Think of the charged particle basically a pulse of charge. The bigger transistors are the bigger capacitance are and the more charge you need to flip anything. Any potential damage it could cause to the chip would also increase. I didn't found anyone trying to make "same" chip in significantly different process.
simne 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Bold No. CMOS technology have one drawback - it is prone to latch up by ionization, because it have The parasitic p-n-p-n thyristor (it is locked in wrong state, to reset must do full power off). Rad-hardened designs have to deal with this, they used special type of die material and clamping diodes, so their technology essentially different from civilian designs.

toast0 4y ago

> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Maybe? But CPU cost basically doesn't matter compared to launch cost. Power budget given the required computing needs during critical sections of the mission is probably the biggest priority after reliability. Modern cpus are good at compute/watt, but not necessarily at low watts at low load. No idea re: feature size, for cosmic rays and dram, it was thought that shrinking beyond some point was going to increase failures dramatically, but then it was fine. But in space radiation is more than cosmic rays.

shagie 4y ago

> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Power constraints and heat dissipation constraints. https://arstechnica.com/science/2019/11/space-grade-cpus-how-do-you-send-more-computing-power-into-space/3/ https://arstechnica.com/science/2019/11/space-grade-cpus-how... > BAE RAD5545 is probably the most powerful radiation-hardened processor available today. Fabricated in the 45nm process, it is a 64-bit quad-core machine clocked at 466MHz with power dissipation of up to 20 Watts—and 20 Watts is a lot. A Quad Core i5 sitting in a 13-inch MacBook Pro 2018 is a 28 Watt processor. It can heat its thin aluminum chassis to really high temperatures up to a point where it becomes an issue for some users. Under more computationally intensive workloads, fans immediately kick in to cool the whole thing down. The only issue is that, in space, fans would do absolutely nothing, because there is no air they could blow onto a hot chip. The only possible way to get heat out of a spacecraft is through radiation, and that takes time. Sure, heat pipes are there to take excessive heat away from the processor, but this heat has to eventually go somewhere. Moreover, some missions have tight energy budgets, and they simply can’t use powerful processors like RAD5545 under such restrictions. That’s why the European GR740 has power dissipation at only 1.5 Watts. It’s not the fastest of the lot, but it is the most efficient. It simply gives you the most computational bang per Watt. The HPSC with 10 Watt power dissipation comes in at a close second, but not always.

nynx 4y ago
45nm is massive for a high-performance processor. Rad-hardening compute is frankly overrated. Have multiple and compare state at a high-rate.
- shagie 4y ago
  But you can't power multiple on the energy budget that you've got. Perseverance is running on 110 watts ( https://mars.nasa.gov/mars2020/spacecraft/rover/electrical-power/ https://mars.nasa.gov/mars2020/spacecraft/rover/electrical-p... ). The RAD5545 uses 20 watts of that budget. Tripling it means it doesn't have enough energy to power the rest of the rover. The Mars MAVEN ( https://spaceflight101.com/maven/spacecraft-information/ https://spaceflight101.com/maven/spacecraft-information/ ) is using a RAD-750 which uses 10 watts of power ( https://en.wikipedia.org/wiki/RAD750 https://en.wikipedia.org/wiki/RAD750 ) (also used in the JWST). The RAD-750... > The processor can endure radiation doses that are a million times more extreme than what is considered fatal to humans. And while you may argue "yes, that seems a bit excessive" - the goal isn't "it can run in those extremes" but rather... > Also, RAD750 will not suffer more than one event requiring interventions from Earth over a 15-year period. > “The RAD750 card is designed to accommodate all those single event effects and survive them. The ultimate goal is one upset is allowed in 15 years. An upset means an intervention from Earth — one ‘blue screen of death’ in 15 years. We typically have contracts that (specify) that,” said Vic Scuderi BAE Business Manager. ... because it can't be replaced easily. From Wikipedia: > The CPU can withstand an absorbed radiation dose of 2,000 to 10,000 grays
  - incrudible 4y ago
    I do not buy the power argument. A modern chip is orders of magnitude more power efficient, especially at low voltage. You could easily have multiples of these within the same power budget.
    - ilyt 4y ago
      But smaller size increases the chance for event (which might be compensated) but also increases chance for fatal damage to happen. The radiation in space is not dangerous because it just produces a bit of current that can flip a bit; it is dangerous because it is strong enough to bump a bunch out of their position in silicon crystal, causing permanent damage that will accumulate over time. And when your feature size is starting to measure in <100 atoms it would be easy for single high energy event to break whole core.

LargeTomato 4y ago

>With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Nasa needs redundancy. Say we ran a program in triplicate, one on each core, and compared the outputs. We still don't have redundancy here because the chip can still fail in a way that will cause problems for all three cores. >My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger). Larger gates tend to be more resilient to radiation. I don't know exactly why. The fabrication tech is also important. Some types of chip manufacturing processes results in more resilient chips. I'm sorry but I don't know enough about it to elaborate further.

afiori 4y ago
Not an expert but essentially radiations can produce electrons in random places flipping one or more transistors unexpectedly. Larger transistors need more electrons so they are slightly more resistant.
- denton-scratch 4y ago
  Because larger transistors need more electrons, they also need more power to switch. I guess that circuitry made from valves/vacuum tubes might provide high radiation resistance?
  - ilyt 4y ago
    I mean, you could just use big transistors
- geomark 4y ago
  That's single event upset (SEU). The other radiation issue is total dose. That's when charge gradually builds up in insulating gates due to ionizing radiation. It's permanent, and eventually reaches the point that the transistor is always on so has a permanent fault. One of the factors is collection area, so larger gates are not less susceptible because they have a larger collection area. But if they run at a higher voltage that can make them more tolerant to total dose.

numpad0 4y ago

> couldn't NASA use these for redundancy? > how much more resilient are older processes with larger feature size compared to modern 6/7nm ? If I may paraphrase your questions, I think you are trying to ask "isn't rad hardening a bit overrated? are space chips that good?" - and a Wikipedia edit[1] that has kept most of its original form for more than 15 years have been answering that question thanklessly: > Hardened chips are often manufactured on insulating substrates instead of the usual semiconductor wafers. Silicon oxide (SOI) and sapphire (SOS) are commonly used. While vanilla chips can withstand between 5 and 10 krad, SOI and SOS can survive doses many orders of magnitude greater. So the answer is, if 10krad(in lifetime) and [unspecified] events/seconds is enough for your requirements, maybe you don't need rad-hard chips. If your requirements are going to be magnitude grater(you can math it from data), then you might want it, and yes, there are differences in orders of magnitudes. 1: https://en.wikipedia.org/w/index.php?title=Radiation_hardening&oldid=46164991 https://en.wikipedia.org/w/index.php?title=Radiation_hardeni...

ilyt 4y ago

> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Think shuttle had 3 separate computers running same code and having mechanism to vote out the one giving bad output ? There are also some automotive ARMs that are basically 2 cores shifted physically 90 degrees running lockstep and some logic to reset if they disagree > My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger). I'd imagine by a lot. Think of the charged particle basically a pulse of charge. The bigger transistors are the bigger capacitance are and the more charge you need to flip anything. Any potential damage it could cause to the chip would also increase. I didn't found anyone trying to make "same" chip in significantly different process.

simne 4y ago

> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Bold No. CMOS technology have one drawback - it is prone to latch up by ionization, because it have The parasitic p-n-p-n thyristor (it is locked in wrong state, to reset must do full power off). Rad-hardened designs have to deal with this, they used special type of die material and clamping diodes, so their technology essentially different from civilian designs.