5 ms·

I wonder how hard it is to just sell a GPU and say it's CUDA compatible. Google built their own toolchain over PTX, AMD could do the same, and have CUDA compati

by ece 4y ago

I wonder how hard it is to just sell a GPU and say it's CUDA compatible. Google built their own toolchain over PTX, AMD could do the same, and have CUDA compatibility if they wanted. I think the difference here just might be that Google's still buying A100s, while AMD wouldn't be. HIP/ROCm support should absolutely be better supported on all AMD hardware for more adoption, instead it seems to barely register like OpenACC or Vulkan compute. Intel might have better luck with OpenAPI.

my123 4y ago
For PTX: For sm_70 onwards (which is the arch that comes with tensor cores) NVIDIA made the task significantly harder. Those newer architectures use a separate instruction pointer per thread/lane, for notably supporting C++ atomics across threads in the same warp without deadlocks. This doesn't match the semantics present on AMD GPUs. For HIP/ROCm: I think that they need an abstraction layer that can make a single slice of binary code that is usable across multiple gens. Compounded by the fact that different dies have different binary slices on the AMD side, so that 6800 XT and 6700 XT run different code slices. ROCm only supports Navi21 cards for RDNA2, not the other ones... For oneAPI, OpenCL SPIR-V fulfills that role.