This is true for off-die ECC (i.e the kind that computes ECC between chips using a separate chip) however on-die ECC (the ECC logic and parity memory being incl

This is true for off-die ECC (i.e the kind that computes ECC between chips using a separate chip) however on-die ECC (the ECC logic and parity memory being included in the memory chip itself) like what DDR5 will have doesn't have this bandwidth issue. It causes the dies to cost slightly more but otherwise largely results in the same performance as non-ECC memory. In the GPU space, this is why HBM2 memory doesn't really have a performance difference between ECC and non-ECC memory.