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A modern circuit simulator, that has a fully featured programable API, that can be run from a real modern programming language, would be a dream. Every simulato

A modern circuit simulator, that has a fully featured programable API, that can be run from a real modern programming language, would be a dream. Every simulator i have used has been pretty limited in that way, or at least those features were not well advertized. Even the insanely expensive ones. I mean the most expensive ones (like $100K liscense type deals, like Cadence) are if anything even less modern from a user interaction perspective. My first academic paper (https://www.oxinabox.net/publications/White2015PsoTransistorSizing.pdf https://www.oxinabox.net/publications/White2015PsoTransistor...) was based on doing a search over parameters for the transistors being used in a circuit. The way that whole thing work was by string mangling the netlist file to update the parameters. Triggering the simulator on the commandline. Getting it to output a CSV of the signals. Parsing that CSV, and detecting edges and then measuring timing that way. Then throwing it at a particle swarm optimizer to fine a new one. That sucks from a user experience. It's a super cool way to solve problems though. that would be so easy with a real API. Further, with julia being a differnetiable programming language, rather than having to use a particular swarm optimizer to search, I could have been differentiating it, and using some sophisticated gradient descent like LBGFS etc. I hope that some of the general tools like this will be an outcome of this project.

eternauta3k 6y ago
Have you looked into Spectre's interactive mode? You can send SKILL commands to change parameters and rerun simulations. It's not documented, though.
throwaway9870 6y ago
There was a simulator called HSIM that I used 20 years ago to do what you describe. It had a C api that I integrated with. It was more of a fast Spice rather than equivalent to HSPICE or Spectre. I coupled it with a little mini-language I wrote to do easily scriptable regression tests for our system. I believe Synopsys bought the company.
jacquesm 6y ago
That is an interesting optimization trick, essentially a brute force search over a parameter space in order to minimize silicon area, I am assuming this was for cells that were going to be replicated many times on the same die?
- oxinabox 6y ago
  Something like that is the idea. Silicon area is what costs money. Use as little as possible while still being fast enough to beat the clock-rate of your system. PSO's are way better than brute force. but yeah. It was a purely academic work for a masters level CS unit. I had just finished a masters level electrical engineering unit on silicon circuit design. Where the final project was to design an adder that minimized silicon used (and thus cost) while also being faster enough. And the hard bit is that you want big thick doped regions for high conductivity, but also the bigger the area the more paracidic capacitance. And so there are some tricks the to find good sizes, like progressive sizing and stuff. But afaik there is no actual answer, at least not one we ever learned. So a lot of trial and error went into it. It was a hard project. And so then I did this CS unit where the project was "Do something interesting with a particle swarm optimizer". And i was like "lets solve this". and once I saw the results, i was like "this is actually really good", and so the lecturer and I wrote a paper about it. It is a real problem. Minimizing silicon area subject to speed. I bet the big integrated designers have there own tricks for it that i don't know about. To do it really well you need to miminal the real area so also need to solve layout (which is a cool cutting and packing problem). (and ther are also nth order effects, like running traces over things can cause slow downs, because electromagnetism reasons) I bet a bunch of folk on HN know this problem much better than i do though. probably something bad in my solution, but i think it illustrates the utility
  - jacquesm 6y ago
    Thank you for writing it up and posting it here, one of the more interesting comment threads.
  - kayson 6y ago
    Very cool paper. Your observations in V.B.4 are pretty well understood in circuit design. If you've not heard of it, you might be interested in https://en.wikipedia.org/wiki/Logical_effort https://en.wikipedia.org/wiki/Logical_effort. Turns out the optimum scaling for propagation delay is e (natural log constant), but I don't know if I ever learned anything about the optimum for area. Now that everyone is using finfet processes, the layout part is pretty easy to solve because transistor widths have to be a certain number of fins and the layout is extremely regular. One thing your analysis didn't include, which actually ends up being quite significant, is the extra capacitance caused by the wires between transistors. This changes the sizing requirements substantially. I've done some custom logic cell design, and I always had to use a lot of trial and error, though generally I was concerned more with speed than area. I'm not sure exactly what the development process is at my current employer, but it seems like its a lot of manual work. I'm guessing they set area targets based on experience and attempt to maximize speed where possible. Ultimately, everything gets placed and routed by a computer anyways!
multiply 6y ago
A lot of semi companies have built their own simulation environments because the EDA vendor's provided tools are very limited in what they can do and difficult to use. Many users go to Python, Excel or MATLAB because the programming/math capabilities of the EDA tools are inadequate. Over time these home-grown environments become a burden and the developer disowns it and it becomes a headache. The EDA tools have no ecosystem you can hook into and they don't really care about the user trying to put the simulators into a flow to solve their problem. It is a bunch of point tools each with their own embedded interpreter that don't play together. I sure hope there is a plan to create a better set of tools so I can write custom netlist checks and do something novel (like get derivatives out of the simulator) and in-memory (no slow disks) and run custom Julia checks during simulation. Julia is a much better match because running Python or MATLAB code within the simulator is way too slow. I'll keep watch for sure.
- kayson 6y ago
  It's an absolute nightmare. Cadence added support for Matlab calculations on simulator outputs, but its clunky and inconsistent. Don't even get me started on how long it takes to do basic calculations on numbers that should already be in memory...
  - multiply 6y ago
    My worst experience was doing a simple min/max of each signal took 7x longer than the simulation. I'd be so happy to toss TCL in the trash. I spent a long time debugging because TCL expr doesn't do -2^2 correctly. The error messages don't tell you the line number and I found no good way to debug. Things like that are just the tip of the iceberg of time wasted fighting with arcane tools. I suppose others have their own stories.
    - kbr2000 6y ago
      In Tcl's expr: ^ stands for bitwise XOR: so [expr {-2^2}] results in -4 * stands for exponentiation: so [expr {-2*2}] results in 4 Both seem correct to me, taking into account how integers are represented in binary (two's complement for the negative ones). With regards to debugging dynamic programming languages, it is different as compared to their static counterparts, since much is delayed to happen at runtime (as opposed to at compilation time). But it also opens up possibilities (like introspection, ability to intervene in the scripts while they run, ...). It requires a different mindset.
ur-whale 6y ago
Talking about this - sorry for the slight OT - I really wish Linear would consider OpenSourcing LTSpice. I mean ... it's a really nice tool, they are giving away from free anyways ... if they OpenSourced it, the kind of feature you describe here (and which I've been sorely missing as well) would be a no-brainer to implement. Not to mention all the other enhancements the community could and would bring to it.

eternauta3k 6y ago

Have you looked into Spectre's interactive mode? You can send SKILL commands to change parameters and rerun simulations. It's not documented, though.

throwaway9870 6y ago

There was a simulator called HSIM that I used 20 years ago to do what you describe. It had a C api that I integrated with. It was more of a fast Spice rather than equivalent to HSPICE or Spectre. I coupled it with a little mini-language I wrote to do easily scriptable regression tests for our system. I believe Synopsys bought the company.

jacquesm 6y ago

That is an interesting optimization trick, essentially a brute force search over a parameter space in order to minimize silicon area, I am assuming this was for cells that were going to be replicated many times on the same die?

oxinabox 6y ago
Something like that is the idea. Silicon area is what costs money. Use as little as possible while still being fast enough to beat the clock-rate of your system. PSO's are way better than brute force. but yeah. It was a purely academic work for a masters level CS unit. I had just finished a masters level electrical engineering unit on silicon circuit design. Where the final project was to design an adder that minimized silicon used (and thus cost) while also being faster enough. And the hard bit is that you want big thick doped regions for high conductivity, but also the bigger the area the more paracidic capacitance. And so there are some tricks the to find good sizes, like progressive sizing and stuff. But afaik there is no actual answer, at least not one we ever learned. So a lot of trial and error went into it. It was a hard project. And so then I did this CS unit where the project was "Do something interesting with a particle swarm optimizer". And i was like "lets solve this". and once I saw the results, i was like "this is actually really good", and so the lecturer and I wrote a paper about it. It is a real problem. Minimizing silicon area subject to speed. I bet the big integrated designers have there own tricks for it that i don't know about. To do it really well you need to miminal the real area so also need to solve layout (which is a cool cutting and packing problem). (and ther are also nth order effects, like running traces over things can cause slow downs, because electromagnetism reasons) I bet a bunch of folk on HN know this problem much better than i do though. probably something bad in my solution, but i think it illustrates the utility
- jacquesm 6y ago
  Thank you for writing it up and posting it here, one of the more interesting comment threads.
- kayson 6y ago
  Very cool paper. Your observations in V.B.4 are pretty well understood in circuit design. If you've not heard of it, you might be interested in https://en.wikipedia.org/wiki/Logical_effort https://en.wikipedia.org/wiki/Logical_effort. Turns out the optimum scaling for propagation delay is e (natural log constant), but I don't know if I ever learned anything about the optimum for area. Now that everyone is using finfet processes, the layout part is pretty easy to solve because transistor widths have to be a certain number of fins and the layout is extremely regular. One thing your analysis didn't include, which actually ends up being quite significant, is the extra capacitance caused by the wires between transistors. This changes the sizing requirements substantially. I've done some custom logic cell design, and I always had to use a lot of trial and error, though generally I was concerned more with speed than area. I'm not sure exactly what the development process is at my current employer, but it seems like its a lot of manual work. I'm guessing they set area targets based on experience and attempt to maximize speed where possible. Ultimately, everything gets placed and routed by a computer anyways!

multiply 6y ago

A lot of semi companies have built their own simulation environments because the EDA vendor's provided tools are very limited in what they can do and difficult to use. Many users go to Python, Excel or MATLAB because the programming/math capabilities of the EDA tools are inadequate. Over time these home-grown environments become a burden and the developer disowns it and it becomes a headache. The EDA tools have no ecosystem you can hook into and they don't really care about the user trying to put the simulators into a flow to solve their problem. It is a bunch of point tools each with their own embedded interpreter that don't play together. I sure hope there is a plan to create a better set of tools so I can write custom netlist checks and do something novel (like get derivatives out of the simulator) and in-memory (no slow disks) and run custom Julia checks during simulation. Julia is a much better match because running Python or MATLAB code within the simulator is way too slow. I'll keep watch for sure.

kayson 6y ago
It's an absolute nightmare. Cadence added support for Matlab calculations on simulator outputs, but its clunky and inconsistent. Don't even get me started on how long it takes to do basic calculations on numbers that should already be in memory...
- multiply 6y ago
  My worst experience was doing a simple min/max of each signal took 7x longer than the simulation. I'd be so happy to toss TCL in the trash. I spent a long time debugging because TCL expr doesn't do -2^2 correctly. The error messages don't tell you the line number and I found no good way to debug. Things like that are just the tip of the iceberg of time wasted fighting with arcane tools. I suppose others have their own stories.
  - kbr2000 6y ago
    In Tcl's expr: ^ stands for bitwise XOR: so [expr {-2^2}] results in -4 * stands for exponentiation: so [expr {-2*2}] results in 4 Both seem correct to me, taking into account how integers are represented in binary (two's complement for the negative ones). With regards to debugging dynamic programming languages, it is different as compared to their static counterparts, since much is delayed to happen at runtime (as opposed to at compilation time). But it also opens up possibilities (like introspection, ability to intervene in the scripts while they run, ...). It requires a different mindset.

ur-whale 6y ago

Talking about this - sorry for the slight OT - I really wish Linear would consider OpenSourcing LTSpice. I mean ... it's a really nice tool, they are giving away from free anyways ... if they OpenSourced it, the kind of feature you describe here (and which I've been sorely missing as well) would be a no-brainer to implement. Not to mention all the other enhancements the community could and would bring to it.