I've kind of always felt that synthesizable Verilog/SystemVerilog was good, but the verification side was just too complex and had too much bloat. Testing hardw

I've kind of always felt that synthesizable Verilog/SystemVerilog was good, but the verification side was just too complex and had too much bloat. Testing hardware with Python (like Cocotb) feels more on the right track as a high level UI. But easily pluggable APIs for foreign SW languages are key as well. Hardware software co-design is only becoming more important.