6 ms·
The correct term to use here is blocking. The hardware bus locks finish in a bounded amount of time and allow the other processors to eventually make progress.
by denormalfloat 7y ago
The correct term to use here is blocking. The hardware bus locks finish in a bounded amount of time and allow the other processors to eventually make progress.
- amelius 7y agoThat is a good distinction, but I'm not sure if it's always true. A peripheral device on a shared bus could still hold the lock for an undetermined time.
- jasonwatkinspdx 7y agoWhen people say "lock the bus" they don't literally mean it's like there's a single bus and mutex. Atomic operations execute atop the cache consistency protocol, which typically looks like: https://en.wikipedia.org/wiki/MOESI_protocol https://en.wikipedia.org/wiki/MOESI_protocol It is indeed true that atomic operations will execute in a bounded time, and processors generally provide fairness guarantees as well.
- amelius 7y agoYes, and the cache hierarchy ultimately depends on the memory bus. I suppose this bus, which may be shared with many other devices, doesn't always have bounded-time guarantee.
- gpderetta 7y agoEven to main memory there is not necessarily a single memory bus. Intracore or even intrasocket synchronization need not (and usually doesn't) go through main memory anyway.
- amelius 7y agoTrue, but some atomic instructions may need to access main memory to complete their operation. Whether shortcuts can be taken in most cases is not relevant for worst-case considerations.
- gpderetta 7y agoSure any memory access might access main memory. There is no special casing for atomic though.
- bonzini 7y agoThey may need to access main memory, but the RMW operation don't happen over the memory bus. The processor appropriates the cache line just like any other memory access, and then operates atomically on the cache line.
- amelius 7y agoAnd what if the cache line is full/dirty?
- bonzini 7y agoThe cache coherency protocol takes care of that. In other words the first part is just a memory load and can vary from 0 to a few hundred clock cycles, the second is local to the processor and has a more or less fixed cost. The worst-case execution time is completely dominated by the first part, the best case instead is dominated by the second.
- jasonwatkinspdx 7y agoI'd suggest reading the wiki articles about it for an introduction, and Ch 5 of https://www.amazon.com/Computer-Architecture-Quantitative-John-Hennessy/dp/012383872X https://www.amazon.com/Computer-Architecture-Quantitative-Jo... for a detailed understanding. Right now you're asserting things about all this, while not being familiar with relatively basic aspects of how it works.
- gpderetta 7y agoYes. Even better than that, atomic instructions are usually completely local to a core. I think that the only interaction with with the coherency protocol is that a core is guaranteed to be able to hold a cache in exclusive mode long enough to execute an RMW (and even that it is not really required, but useful to guarantee forward progress).
- namibj 7y agoSince NVLink2 and POWER9, even a GPU can issue atomics over the bus, which will be executed local to the CPU that owns this cacheline. This is very useful in high-contention write-heavy workloads, like atomic counters or accumulators.