6 ms·

So it is a game over here. Unless Intel can change the microcode to force a page fault in this case.

• bstx 9y ago
  It doesn't make sense for speculatively executed code to throw architecturally visible exceptions. The appropriate behavior would be to not perform speculative loads across protection domains (i.e. the behavior of AMD implementations).
  • j_coder 9y ago
    It would make sense if it was the only alternative as the kernel can handle it. The appropriate behavior is to remove all traces of the speculative execution including cache hits.
    • GrayShade 9y ago
      Is that even possible? The data that would need to be removed from the cache has already evicted other cache lines, and that re-fetching those might have observable effects, like the timing.