6 ms·
How do you manage cached and uncached memory accesses? There has been some discussion lately on the mailing lists about this
by vanjoe 9y ago
How do you manage cached and uncached memory accesses? There has been some discussion lately on the mailing lists about this
- Dolu 9y agoCached an uncached memory access are currently staticaly specified by range : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/VexRiscv/demo/Briey.scala#L234 https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s... From 0xF000000 to 0xFFFFFFFF access will be uncached.