5 ms·
"Chip designers are under so much pressure to deliver ever-faster CPUs that they’ll risk changing the meaning of your program, and possibly break it, in order t
by drivebyacct 16y ago
"Chip designers are under so much pressure to deliver ever-faster CPUs that they’ll risk changing the meaning of your program, and possibly break it, in order to make it run faster"
Uh huh. Let me know when that happens.
- terminus 16y agoAlready. The article mentions read, write ordering. That is essentially about in what order other processors see reads, writes being done by this processor: thus if procA does a bunch of writes will procB see them in the order (program order) in which they were done or in a different other order. There can be other interleavings when you introduce read into the mix. Architectures like the late lamented Alpha (this is around late 90's) had fairly weak ordering requirements so you needed explicit memory barriers to tell the processor that you needed ordering preserved (think spinlocks for instance.) Mainstream processors (x86/x86-64) have always had strict write ordering but not read ordering. Let's see how long that lasts.