5 ms·
Designing hardware is done by Visio and Excel not Verilog. Verilog is just an implementation. :) Added: Visio is to draw timing diagram, block diagram, and flo
by codebook 10y ago
Designing hardware is done by Visio and Excel not Verilog.
Verilog is just an implementation. :)
Added: Visio is to draw timing diagram, block diagram, and flow chart. Excel is used for designing FSM next state logic / output.
- trevortheblack 10y agoIn my experience it's visio and Matlab. You need to prove that you can get a certain performance with a matlab algorithm, then you spend a week writing it into verilog. Oh, and as someone whose bread and butter is ICs, I go out of my way to avoid creating FSMs. They're slow, difficult to debug, and hard to pass on to your successor.
- moftz 10y agoInteresting, in my digital design and microcontroller classes, they have been beating FSMs into our heads since day one. I knew there were a few projects where I knew it wasn't totally necessary to do but used a FSM to get the checkbox on the rubric but there were many designs where I had no clue how I could do it without one and without making the code highly complex.